CCD Process

Highlights of our tunable process include low dark current, excellent CTE, and very good yield

DALSA Semiconductor's 150mm C25 2.5µm CCD process offers buried channel or surface channel operation at up to 15 volts with either two or three polysilicon layers. A modular processing approach allows our foundry customers to adjust process parameters for the most demanding requirements on CTE, charge storage capacity and low dark current. Scanner photolithography permits integration of wafer scale devices. We offer advanced technology such as stitching for large devices and more.

DALSA is proud that our base process is fully tunable. Customers specify the buried channel and barrier implants that suit the application. Channel stops, anti-blooming implants, or other special features can be added. Successful projects have included PMOS CCDs for radiation hardness, very high resolution devices (4k x 4k), and high-resistivity devices.

DALSA-built image sensors on the Mars Rovers captured the highest-resolution images
ever taken of another planet. Typical applications for these products are in scientific, industrial, or even space deployments. Custom variants of this process supply many of the image sensors used in the industry-leading digital cameras of DALSA Corporation's Machine Vision division. NASA's JPL chose DALSA to fabricate the image sensors on the Mars Rovers, which captured the highest-resolution images ever taken of another planet.

To support all our customers' custom CCD processes, we offer a wide range of services from mask manufacturing to complete device characterization.

DALSA Semiconductor operates its CCD Wafer Foundry Service as an independent arm from any of the other DALSA Corporation group of Business Units. Customer information and data confidentialty is assured.

Process Capability Parameters

C25 CCD Process
Wafer Size	150mm (Max. die 10x10cm)
Poly Layers	2 or 3
Poly Overlaps	0.5µm
Metal	Single / Double / Triple
Projection Aligner	2.5µm 1X (MPA-600)
Maximum Operating Voltage	15V
Charge Transfer Efficiency (CTE)	> 99.999%
Dark Current	Low (< 1nA/cm2 )
Other	PCM Electrical Wafer Acceptance Wafer Probe Testing Surface and Buried Channel Operation Customizable Process Customized Starting Material Short cycle time
Special Options	Mix & Stitch of multiple stepper fields PMOS CCD for rad-hard High Resistivity CCDs (100Ω-cm to 10 kΩ-cm ) Patent pending Ti/TiN metalisation for high T° post-processing

Process Data

Datasheet: C25 Process Datasheet

Support Data

Design Rules: CCD 2.5, 3.0µm NMOS Buried-Channel Double/Triple-Poly, Double/Triple Metal Process. New updated design rules available, with significantly expanded details and capabilities. Contact DALSA Semiconductor to receive the expanded document.

For more information, contact Sales.